ASICLAND Develops Next-Generation Packaging Utilizing 'Silicon Bridge'
▶ Cost Reduction Goals
▶ Utilization of Heat Spreaders
[Sungmo Kang, a manager at ASICLAND, explains CoWoS.]
ASICLAND is developing a next-generation packaging solution that improves the costs associated with TSMC’s Chip-on-Wafer-on-Substrate (CoWoS). This is achieved through a combination of Re-Distribution Layer (RDL) interposers, silicon (Si) bridges, and heat spreaders. ASICLAND believes this approach will enhance performance, power efficiency, and size.
Sungmo Kang, a manager at ASICLAND, presented on "TSMC Advanced Packaging & ASICLAND Turnkey Solutions" at the 'Semiconductor Hybrid Bonding Conference' held at Posco Tower in Seoul on the 26th of last month, hosted by 《The Elec》.
Kang stated, "Chip-on-Wafer-on-Substrate (CoWoS) offers improvements in performance and power efficiency compared to integrated fan-out (InFO) and organic substrate packages. It also has the advantage of flexible interposer size adjustment." He added, "We are developing next-generation packages that improve the cost of Si interposers."
CoWoS, as explained by Kang, is a type of advanced packaging developed by the foundry company TSMC. It involves processes utilizing Si interposers and through-silicon vias (TSV). The interposer connects the logic die with high-bandwidth memory (HBM). Representative semiconductors produced using CoWoS include NVIDIA’s A100 and H100, as well as Intel’s Gaudi. CoWoS is broadly divided into CoWoS-S (Si interposer), CoWoS-R (RDL interposer), and CoWoS-L (LSI + RDL interposer).
CoWoS-S is a typical CoWoS package where the logic die and HBM are mounted on a Si interposer. CoWoS-R applies an RDL interposer and InFO, offering superior cost competitiveness compared to CoWoS but lacking die-to-die interconnection. CoWoS-L combines the advantages of CoWoS-S and InFO, reducing overall costs through the RDL interposer and supporting interconnection between SoCs and HBM with a local silicon interposer (LSI).
[The advanced package being developed by ASICLAND. <Source: ASICLAND> ]
ASICLAND is developing an advanced package that uses an RDL interposer for cost reduction. The HBM and SoCs are placed on the RDL interposer, with die-to-die interconnection achieved using a silicon bridge. Additionally, a heat spreader is incorporated to reduce thermal output, improving performance and power efficiency. This new packaging development is expected to have a positive impact on customer acquisition.
ASICLAND is the only TSMC design house in Korea. Since being selected as a TSMC Value Chain Aggregator (VCA) in 2019, the company has experienced rapid growth each year. ASICLAND also aims to be listed on the KOSDAQ market in the second half of this year. The funds raised through the listing will be used to explore global market opportunities.
ASICLAND Develops Next-Generation Packaging Utilizing 'Silicon Bridge'
▶ Cost Reduction Goals
▶ Utilization of Heat Spreaders
[Sungmo Kang, a manager at ASICLAND, explains CoWoS.]
ASICLAND is developing a next-generation packaging solution that improves the costs associated with TSMC’s Chip-on-Wafer-on-Substrate (CoWoS). This is achieved through a combination of Re-Distribution Layer (RDL) interposers, silicon (Si) bridges, and heat spreaders. ASICLAND believes this approach will enhance performance, power efficiency, and size.
Sungmo Kang, a manager at ASICLAND, presented on "TSMC Advanced Packaging & ASICLAND Turnkey Solutions" at the 'Semiconductor Hybrid Bonding Conference' held at Posco Tower in Seoul on the 26th of last month, hosted by 《The Elec》.
Kang stated, "Chip-on-Wafer-on-Substrate (CoWoS) offers improvements in performance and power efficiency compared to integrated fan-out (InFO) and organic substrate packages. It also has the advantage of flexible interposer size adjustment." He added, "We are developing next-generation packages that improve the cost of Si interposers."
CoWoS, as explained by Kang, is a type of advanced packaging developed by the foundry company TSMC. It involves processes utilizing Si interposers and through-silicon vias (TSV). The interposer connects the logic die with high-bandwidth memory (HBM). Representative semiconductors produced using CoWoS include NVIDIA’s A100 and H100, as well as Intel’s Gaudi. CoWoS is broadly divided into CoWoS-S (Si interposer), CoWoS-R (RDL interposer), and CoWoS-L (LSI + RDL interposer).
CoWoS-S is a typical CoWoS package where the logic die and HBM are mounted on a Si interposer. CoWoS-R applies an RDL interposer and InFO, offering superior cost competitiveness compared to CoWoS but lacking die-to-die interconnection. CoWoS-L combines the advantages of CoWoS-S and InFO, reducing overall costs through the RDL interposer and supporting interconnection between SoCs and HBM with a local silicon interposer (LSI).
[The advanced package being developed by ASICLAND. <Source: ASICLAND> ]
ASICLAND is developing an advanced package that uses an RDL interposer for cost reduction. The HBM and SoCs are placed on the RDL interposer, with die-to-die interconnection achieved using a silicon bridge. Additionally, a heat spreader is incorporated to reduce thermal output, improving performance and power efficiency. This new packaging development is expected to have a positive impact on customer acquisition.
ASICLAND is the only TSMC design house in Korea. Since being selected as a TSMC Value Chain Aggregator (VCA) in 2019, the company has experienced rapid growth each year. ASICLAND also aims to be listed on the KOSDAQ market in the second half of this year. The funds raised through the listing will be used to explore global market opportunities.